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4.4.1
Register Write Request
During a register write request, bits 12 through 8 contain a five-bit address, and bits 7 through 0 contain the data value to be
written. Writable registers are defined in Table 3 .
The response to a register write operation is shown in Table 27 . The response is transmitted on the next SPI message if and
only if all of the following conditions are met:
? No SPI Error is detected (Reference Section 4.5.1 )
? No MISO Error is detected (Reference Section 4.5.2 )
? The ENDINIT bit is cleared (Reference Section 3.1.6.3 )
? This applies to all registers with the exception of the DEVCTL register (Only Bits 6 and 7 can be modified)
? No Invalid Register Request is detected (Reference Section 4.5.3.2 )
If the above conditions are met, the device responds to the register write request as shown in Table 27 . Otherwise, the device
Responds as specified in Section 4.5 .
Register write operations do not occur internally until the transfer during which they are requested has been completed. In the
event that a SPI Error is detected during a register write transfer, the write operation is not completed.
4.4.2
Register Read Request
During a register read request, bits 12 through 8 contain the five-bit address for the register to be read. Bits 7 through 0 must
be logic ‘0’. Readable registers are defined in Table 3 .
The response to a register read operation is shown in Table 27 . The response is transmitted on the next SPI message if and
only if all of the following conditions are met:
? No SPI Error is detected (Reference Section 4.5.1 )
? No MISO Error is detected (Reference Section 4.5.2 )
? No Invalid Register Request is detected (Reference Section 4.5.3.2 )
If the above conditions are met, the device responds to the register read request as shown in Table 27 . Otherwise, the device
responds as specified in Section 4.5 .
4.5
Exception Handling
The following sections describe the conditions and the device response for each detectable exception. In the event that mul-
tiple exceptions exist, the exception response is determined by the priority listed in Table 30 .
Table 30. SPI Error Response Priority
Effect on Data
Error Priority
Exception
SPI Data
Arming Output
PCM Output
1
2
3
4
5
6
7
8
SPI Error
SPI MISO Error
Invalid Request
DEVINIT Bit Set
DEVRES Error
CRC Error
Self Test Error
Offset Monitor Error
Error Response
Error Response
Error Response
Error Response
Error Response
Error Response
Error Response
Error Response
No Update
No Update
No Update
No Update
No Update
No Update
No Update
No Update
No Effect
No Effect
No Effect
Disabled
Disabled
No Effect
No Effect
No Effect
MMA655x
Sensor
Freescale Semiconductor, Inc.
47
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